DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007

IC LATCH-UP TEST
standard by JEDEC Solid State Technology Association, 11/01/2011

JOINT JEDEC/ECA STANDARD, DEFINING "LOW-HALOGEN" PASSIVES AND SOLID STATE DEVICES (Removal of BFR/CFR/PVC)
standard by JEDEC Solid State Technology Association, 08/01/2011

ADDENDUM No. 1 to JESD35 – GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS
standard by JEDEC Solid State Technology Association, 09/01/1995

HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES
standard by JEDEC Solid State Technology Association, 02/01/1999

COMMON FLASH INTERFACE (CFI)
standard by JEDEC Solid State Technology Association, 09/01/2003

STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 06/01/1996

Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices
standard by JEDEC Solid State Technology Association, 08/01/2012

2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V TOLERANT INPUTS AND OUTPUTS
standard by JEDEC Solid State Technology Association, 06/01/1999

CERAMIC PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGES
standard by JEDEC Solid State Technology Association, 08/01/1993

IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)
standard by JEDEC Solid State Technology Association, 06/01/2004

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE
standard by JEDEC Solid State Technology Association, 10/01/2001